Simulator for Cache Memory Systems on Symmetric Multiprocessors

Computer Organization & Architecture
SMPCache has been selected by William Stallings as simulation tool for the implementation of student projects in the book "Computer Organization & Architecture", 6th edition, 2003, Prentice-Hall.
For more details see Documentation section.

New SMPCache 2.0 !!!        

Español Versión Española


Main characteristics.
To obtain it free of charge.
Simulator versions.
Memory traces.
Creating your own memory trace files.
Utilities for SMPCache.
Universities and Research Centers using SMPCache.
Student Projects from other Universities using SMPCache.
Research Papers from other Universities using SMPCache.


SMPCache is a trace-driven simulator for the analysis and teaching of cache memory systems on symmetric multiprocessors. The simulation is based on a model built according to the architectural basic principles of these systems. The simulator has a full graphic and user-friendly interface, and it operates on PC systems with Windows. The educational experiences, during the last years (from 1998), have demonstrated us the simulator benefits with didactic goals. On the one hand, students have used it for experimenting the different theoretical aspects about cache memories and multiprocessors in the regular courses of Computer Architecture. Some of the parameters that they can study with the simulator are: Program locality; influence of the number of processors, cache coherence protocols, schemes for bus arbitration, mapping, replacement policies, cache size (blocks in cache), number of cache sets (for set associative caches), number of words by block (memory block size), word wide,... On the other hand, students should build a reduced version of the simulator. For that, we give them a set of notes. These notes explain, step by step, all operations and algorithms students should use in order to build a simulator similar to SMPCache. Furthermore, students can use SMPCache as reference for checking their own simulators. The construction of the simulator forces students to know in depth the theoretical considerations about cache memory systems, and particularly on multiprocessor environments (cache coherence, cache coherence protocols,...). In this way, we have observed that students acquire a better and larger knowledge about these aspects. In conclusion, the use of the simulator is an innovation in the practical classes that produces an improvement of the quality in education.

At first, the simulator was conceived as a tool for applying it to teaching of cache memories. However, the potentiality of the developed system has proved its utility on program analysis and design strategies of memory systems on multiprocessors. The previous features enable the simulator to be used in order to understand the design of organizations that run optimally a determinate type of parallel programs or to improve the operating mode of a concrete parallel architecture.

Main characteristics

The simulator offers the configuration possibilities presented in the following table.
Processors in SMP 1, 2, 3, 4, 5, 6, 7 or 8
Cache coherence protocols MSI, MESI (Illinois) or Dragon
Schemes for bus arbitration Random, LRU or LFU
Word wide (bits) 8, 16, 32 or 64
Words by block 1, 2, 4, 8, 16, 32, 64, 128, 256, 512 or 1024
Blocks in main memory 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536, 131072, 262144, 524288, 1048576, 2097152 or 4194304
Blocks in cache 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024 or 2048
Mapping Direct, Set-Associative or Fully-Associative
Cache sets (for set associative caches) 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024 or 2048
Replacement policies Random, LRU, FIFO or LFU
Writing strategies Write-Back (for cache coherence protocols used)
Cache levels in the memory hierarchy 1
References To memory words
Maximum block size 8 KB
Maximum main memory size 32 GB
Maximum cache size (excluded labels, block state bits, counts, etc.) 16 MB
The different choices selected in the simulator for configuring a given architecture may be stored on an ASCII data file for a future loading, so the need of making many selections for configuring the same memory model is avoided. Even more, it is possible to set a default initial configuration for the simulator.

SMPCache shows, using statistical data and several kinds of graphics, interesting measurements like:

  • Number of bus transactions (it depends on cache coherence protocol).
  • Number of block transfers on the bus.
  • Bus traffic taking into account the previous measurements.
  • Number of state transitions (each block in a cache has a state associated with it).
  • Number of state transitions from a particular state to other.
  • Global number of memory accesses, and for types: instruction captures, data readings and data writings.
  • Number of cache hits and misses, as well as hit and miss rate.
  • All these data are shown at very different vision levels, although in all cases, the relation among all the multiprocessor elements is took into account. So, we can realize a simulation:
  • Observing the complete multiprocessor and all the memory blocks.
  • Observing a specific cache and all the memory blocks.
  • Observing the complete multiprocessor, but focusing on a particular block.
  • Observing a specific cache and a particular memory block.
  • There are three kinds of simulation and it is possible to change from one to other without waiting the simulation end:
  • Step by step. The simulation is stopped after every memory access.
  • With breakpoint. The simulation is stopped when a specific number of memory accesses is reached .
  • Complete execution. The simulation is stopped when all the memory traces are finished.
  • It is also possible to abort the simulation at any time, for correcting any architectural detail.

    Instructions to obtain it free of charge

    The simulator is available, with educational and research purposes, for universities and research centers, free of charge. However, a registration is necessary. Then, we will grant to you the right to use, with educational and research purposes (any commercial use is forbidden), the SMPCache simulator. Furthermore, with this registration, user will be notified when new updates arise.

    In order to obtain SMPCache the steps to follow are:

  • Get the SMPCache license.
  • Fill, sign and seal it.
  • Send the license via e-mail (, scanned version of the filled license form) or postal mail (please, see the address in the license form).
  • In a few days, you will receive an e-mail with the requested version of SMPCache (it consists in one Windows executable file, the help files associated, and one collection of memory traces).
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    Simulator versions

    At present, two versions of the simulator are available:
  • Version 1.0: It is the Spanish version of the simulator.
  • Version 2.0: It is the English version of the simulator. New!!!
  • Although both versions are similar, the new version (v 2.0) includes some improvements: improvements in the interface thanks to the use of the new advances in visual languages, correction of some bugs found in the first version, etc. The following section shows some snapshots of both versions.


    These are some snapshots for SMPCache version 1.0 (Spanish version): These are some snapshots for SMPCache version 2.0 (English version):

    Memory traces

    Uniprocessor traces

    You could first study the basic algorithms and concepts that are present in every cache memory system, uniprocessor or multiprocessor. You could consequently configure the SMPCache simulator with a single processor, and use uniprocessor traces. For this first set of experiments you could consider traces of some SPEC’92 benchmarks (Hydro, Nasa7, Cexp, Mdljd, Ear, Comp, Wave, Swm and UComp), according to real tests performed on a MIPS R2000 system. These traces represent a wide variety of “real” application programs, and come from the Parallel Architecture Research Laboratory (PARL), New Mexico State University (NMSU), where they were provided by Nadeem Malik of IBM. These traces, with the correct format for SMPCache, are included in your copy of the simulator. A summary of the traces is given in the following table.
    Floating point
    (double precision)
    Astrophysics: It uses hydrodynamical Navier Stokes equations to calculate galactical jets
    Floating point
    (double precision)
    A collection of 7 program kernels of operations used frequently in NASA applications, such as Fourier transforms and matrix manipulations. For each kernel, the program generates its own input data, performs the kernel and compares the result against an expected result
    Portion of a Gnu C compiler that exhibits strong random behaviour
    Floating point
    (double precision)
    It solves the equations of motion for a model of 500 atoms interacting through the idealized Lennard-Jones potential. It is a numerical program that exhibits mixed looping and random behaviour
    Floating point
    (single precision)
    It simulates the human ear by converting a sound file to a cochleogram using Fast Fourier Transforms and other
    math library functions
    It uses Lempel-Ziv coding for data compression. It compresses an 1 MB file 20 times
    Floating point
    (single precision)
    It solves Maxwell’s equations and electromagnetic particle equations of motion
    Floating point
    (single precision)
    It solves a system of shallow water equations using finite difference approximations on a 256*256 grid
    The uncompress version of Comp


    Multiprocessor traces

    After analysing the basic algorithms and concepts that are present in every cache memory system (uniprocessor or multiprocessor), you could study some theoretical issues related with multiprocessor systems (cache coherence protocols, influence of the number of processors, etc.). In these experiments, you could consequently configure the SMPCache simulator with more than one processor, and use multiprocessor traces with tens of millions of memory accesses (references) for four benchmarks (FFT, Simple, Speech and Weather). These traces were provided by David Chaiken (then of MIT) for NMSU PARL. These traces represent several real parallel applications (FFT, Simple and Weather traces were generated using the post-mortem scheme implemented by Mathews Cherian with Kimming So at IBM). A summary of the traces is shown in the following table.
    Parallel application that simulates the fluid dynamics with FFT
    Parallel version of the SIMPLE application
    Kirk Johnson and David Kranz (both at MIT) are responsible for this trace
    Parallel version of the WEATHER application, which is used for weather forecasting. The serial version is from NASA Space Flight Center, Greenbelt, Md.

    These traces, with the correct format for SMPCache, can be downloaded from the following table. For space reasons, the traces have been compressed: first with WinAce Archiver, and then with WinZip. Therefore, using WinZip, decompress the files in some directory, and you will obtain ".exe" programs. These are SFX archives of WinAce, that is, you should execute these programs because they are self-extracting archives.


    Trace name
    Number of processors
    1   (1,606 KB)

    2   (1,807 KB)

    4   (1,914 KB)

    8   (2,065 KB)
    1   (10,457 KB)

    2   (8,042 KB)

    4   (7,682 KB)

    8   (8,020 KB)
    1   (6,382 KB)

    2   (7,639 KB)

    4   (9,388 KB)

    8   (9,833 KB)
    8   (6,722 KB)

    Creating your own memory trace files

    There are several ways in order to create your own memory trace files:
  • The memory trace files for SMPCache are ASCII data files (with the extension “.prg”), therefore, you can create and edit them using a common text editor. In this way, you can create, for example, memory trace files for teaching purposes (with some special feature). The simulator includes, in its installation directory, some small trace files created by an editor for studying several special cases of the MSI, MESI (Illinois) and Dragon protocols.
  • It is easy to create trace files for basic operations with vectors in C++. The following file is an example of C++ program for generating this type of memory traces: traces.cpp. This file was provided by Fernando Pardo at University of Valencia (Spain).
  • You can create memory traces by other tools or obtain memory traces from other web sites or trace databases, as NMSU PARL. This is the case for the traces in Memory traces section. Then, you can convert these traces to SMPCache format. Please, go to Utilities for SMPCache section in order to find an interesting trace format converter.
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    SMPCache has been selected by William Stallings as simulation tool for the implementation of student projects in the book "Computer Organization & Architecture", 6th edition, 2003, Prentice-Hall (Appendix C: Projects for Teaching Computer Organization and Architecture). This book has been three-time winner of the best Computer Science and Engineering textbook of the year from the Textbook and Academic Authors Association (the last time for the 6th edition, 2003). The Instructor's Resource CD-ROM of this book includes a list of simulation projects plus manual for SMPCache.

    Also, you can get detailed information about the utility of the simulator in the following papers:

    Utilities for SMPCache

    These are some utilities for SMPCache:


    More than 360 Universities and Research Centers already use SMPCache:


    Student Projects from other Universities using SMPCache

    Please, remember that the Instructor's Resource CD-ROM of the book "Computer Organization & Architecture" (6th edition, 2003, Prentice-Hall) includes a large list of simulation projects plus manual for SMPCache (see Documentation section). In this section we include some student projects provided by professors from other Universities:

    Research Papers from other Universities using SMPCache

    In this section we include some research papers that use SMPCache. These papers have been written by researchers from other Universities. For papers written by the SMPCache authors, please, see Documentation section.

    Last update: January 2006
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