/*
   Example of program for generating multiprocessor memory traces for
   SMPCache simulator.
   This program generates traces simulating the copy of one vector to other,
   without considering the instruction accesses (captures of instructions).
   It is easy to change this operation (copy of one vector to other) for
   other operations with vectors.
   This program generates the trace files for configurations with 1, 2, 4
   and 8 processors.
*/

#include <fstream.h>
#include <stdio.h>

const int LVEC  = 1000; // Vector length
const int NPROC =    8; // Maximum number of processors
const int RD    =    2; // It indicates Read
const int WR    =    3; // It indicates Write

// This function writes a memory access with the simulator format.
// It needs the trace file, the memory access type, and the address
void trace(ofstream &file,int type,void *addr)
{
 file << type << " ";
 file.width(8);
 file.fill('0');
 file << hex << (int)addr << endl;
}

int main()
{
 int a[LVEC],b[LVEC];  // Test vectors
 ofstream file[NPROC]; // Files for each processor
 int n,i,proc;
 char fname[33];

 for (n=1;n <= NPROC;n*=2)
 {
   for (proc=0;proc < n;proc++)
   {
     sprintf(fname,"c:\\temp\\trace%d_%d.prg",n,proc+1);
     file[proc].open(fname);
   }
   for (i=0;i < LVEC;i++)
   {
     a[i]=b[i]; // Example of operation
       //proc=n*i/LVEC;    // Consecutive distribution
       proc=i % n;      // Interleaved distribution
       trace(file[proc],RD,&b[i]); // Read from b[i]
       trace(file[proc],WR,&a[i]); // Write to a[i]
   }
   for (proc=0;proc < n;proc++) file[proc].close();
 }
 return 0;
}